r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 66

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 2 CPU
Rev. 2.00 Dec. 09, 2005 Page 42 of 1152
REJ09B0191-0200
Addressing
Mode
Indexed GBR
indirect
TBR duplicate
indirect with
displacement
PC indirect with
displacement
Instruction
Format
@(R0, GBR) The effective address is the sum of GBR value
@@
(disp:8,
TBR)
@(disp:8,
PC)
Effective Address Calculation
and R0.
The effective address is the sum of TBR value
and an 8-bit displacement (disp). The value of
disp is zero-extended, and is multiplied by 4.
The effective address is the sum of PC value and
an 8-bit displacement (disp). The value of disp is
zero-extended, and is doubled for a word
operation, and quadrupled for a longword
operation. For a longword operation, the lowest
two bits of the PC value are masked.
(zero-extended)
(zero-extended)
H'FFFFFFFC
GBR
R0
disp
disp
TBR
PC
2/4
4
×
&
×
+
+
(for longword)
+
PC & H'FFFFFFFC
GBR + R0
+ disp × 4)
PC + disp × 2
+ disp × 4
+ disp × 4
(TBR
TBR
or
Equation
GBR + R0
Contents of
address (TBR
+ disp × 4)
Word:
PC + disp × 2
Longword:
PC &
H'FFFFFFFC +
disp × 4