r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 1159

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Item
Table 10.2 Pin Configuration
10.3.2 Timer Mode Register
(TMDR)
10.3.3 Timer I/O Control Register
(TIOR)
Page Revision (See Manual for Details)
413
423
425
Note added.
Note: For the pin configuration in complementary PWM
Amended.
Amended.
TIOR should be set while TMDR is set in normal
operation, PWM mode, or phase counting mode.
Bit
5
4
mode, see table 10.54 in section 10.4.8,
Complementary PWM Mode.
Bit Name Description
BFB
BFA
Buffer Operation B
Specifies whether TGRB is to operate in
the normal way, or TGRB and TGRD are
to be used together for buffer operation.
When TGRD is used as a buffer register,
TGRD input capture/output compare is not
generated in a mode other than
complementary PWM. TGRD compare
match is generated in complementary
PWM mode. When compare match occurs
during the Tb period in complementary
PWM mode, TGRD is set. Therefore, set
the TGIED bit in the timer interrupt enable
register 3/4 (TIER_3/4) to 0.
Buffer Operation A
Specifies whether TGRA is to operate in
the normal way, or TGRA and TGRC are
to be used together for buffer operation.
When TGRC is used as a buffer register,
TGRC input capture/output compare is not
generated in a mode other than
complementary PWM. TGRC compare
match is generated when in
complementary PWM mode. When
compare match for channel 4 occurs
during the Tb period in complementary
PWM mode, TGFC is set. Therefore, set
the TGIEC bit in the timer interrupt enable
register 4 (TIER_4) to 0.
Rev. 2.00 Dec. 09, 2005 Page 1135 of 1152
REJ09B0191-0200