r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 793

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

In serial reception, the SCIF operates as described below.
1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal
2. The received data is stored in SCRSR in LSB-to-MSB order.
3. The parity bit and stop bit are received.
4. If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1, a receive-FIFO-
Figure 15.9 shows an example of the operation for reception.
synchronization and starts reception.
After receiving these bits, the SCIF carries out the following checks.
A. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only
B. The SCIF checks whether receive data can be transferred from the receive shift register
C. Overrun check: The SCIF checks that the ORER flag is 0, indicating that the overrun error
D. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not
If all the above checks are passed, the receive data is stored in SCFRDR.
Note: When a parity error or a framing error occurs, reception is not suspended.
data-full interrupt (RXI) request is generated. If the RIE bit or the REIE bit in SCSCR is set to
1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the
RIE bit or the REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a
break reception interrupt (BRI) request is generated.
the first is checked.
(SCRSR) to SCFRDR.
has not occurred.
set.
Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Dec. 09, 2005 Page 769 of 1152
REJ09B0191-0200