r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 174

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 5 Interrupt Controller (INTC)
5.8.1
(1)
The contents of the general registers (R0 to R14), global base register (GBR), multiply and
accumulate registers (MACH and MACL), and procedure register (PR), and the vector table
address offset are banked.
(2)
This LSI has fifteen register banks, bank 0 to bank 14. Register banks are stacked in first-in last-
out (FILO) sequence. Saving takes place in order, beginning from bank 0, and restoration takes
place in the reverse order, beginning from the last bank saved to.
5.8.2
(1)
Figure 5.11 shows register bank save operations. The following operations are performed when an
interrupt for which usage of register banks is allowed is accepted by the CPU:
a. Assume that the bank number bit value in the bank number register (IBNR), BN, is i before the
b. The contents of registers R0 to R14, GBR, MACH, MACL, and PR, and the interrupt vector
c. The BN value is incremented by 1.
Rev. 2.00 Dec. 09, 2005 Page 150 of 1152
REJ09B0191-0200
interrupt is generated.
table address offset (VTO) of the accepted interrupt are saved in the bank indicated by BN,
bank i.
Banked Register
Input/Output of Banks
Saving to Bank
Banked Register and Input/Output of Banks
Bank Save and Restore Operations
(c)
BN
+1
Figure 5.11 Bank Save Operations
(a)
Register banks
Bank i + 1
Bank 14
Bank 0
Bank 1
Bank i
:
:
:
:
(b)
R0 to R14
Registers
MACH
MACL
GBR
VTO
PR