r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 181

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

The user break controller (UBC) provides functions that simplify program debugging. These
functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug
programs without using an in-circuit emulator. Instruction fetch or data read/write (bus master
(CPU or DMAC) selection in the case of data read/write), data size, data contents, address value,
and stop timing in the case of instruction fetch are break conditions that can be set in the UBC.
Since this LSI uses a Harvard architecture, instruction fetch on the CPU bus (C bus) is performed
by issuing bus cycles on the instruction fetch bus (F bus), and data access on the C bus is
performed by issuing bus cycles on the memory access bus (M bus). The UBC monitors the C bus
and internal bus (I bus).
6.1
1. The following break comparison conditions can be set.
• Address
• Data
• Bus master when I bus is selected
• Bus cycle
• Read/write
• Operand size
2. In an instruction fetch cycle, it can be selected whether the start of user break interrupt
3. When a break condition is satisfied, a trigger signal is output from the UBCTRG pin.
Number of break channels: two channels (channels 0 and 1)
User break can be requested as the independent condition on channels 0 and 1.
Comparison of the 32-bit address is maskable in 1-bit units.
One of the three address buses (F address bus (FAB), M address bus (MAB), and I address bus
(IAB)) can be selected.
Comparison of the 32-bit data is maskable in 1-bit units.
One of the two data buses (M data bus (MDB) and I data bus (IDB)) can be selected.
Selection of CPU cycles or DMAC cycles
Instruction fetch (only when C bus is selected) or data access
Byte, word, and longword
exception processing is set before or after an instruction is executed.
Features
Section 6 User Break Controller (UBC)
Rev. 2.00 Dec. 09, 2005 Page 157 of 1152
Section 6 User Break Controller (UBC)
REJ09B0191-0200