r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 282

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 8 Bus State Controller (BSC)
8.4.5
RTCSR specifies various items about refresh for SDRAM. RTCSR is initialized to H'00000000 by
a power-on reset and retains the value by a manual reset and in software standby mode.
When RTCSR is written, the upper 16 bits of the write data must be H'A55A to cancel write
protection.
The phase of the clock for incrementing the count in the refresh timer counter (RTCNT) is
adjusted only by a power-on reset. Note that there is an error in the time until the compare match
flag is set for the first time after the timer is started with the CKS[2:0] bits being set to a value
other than B'000.
Initial value:
Initial value:
Rev. 2.00 Dec. 09, 2005 Page 258 of 1152
REJ09B0191-0200
Bit
31 to 8
7
R/W:
R/W:
Bit:
Bit:
Refresh Timer Control/Status Register (RTCSR)
Bit Name

CMF
31
15
R
R
0
0
-
-
30
14
R
R
0
0
-
-
29
13
R
R
0
0
-
-
Initial
Value
All 0
0
28
12
R
R
0
0
-
-
27
11
R
R
0
0
-
R/W
R
R/W
-
26
10
R
R
0
0
-
-
Description
Reserved
These bits are always read as 0.
Compare Match Flag
Indicates that a compare match occurs between the
refresh timer counter (RTCNT) and refresh time
constant register (RTCOR). This bit is set or cleared in
the following conditions.
0: Clearing condition: When 0 is written in CMF after
1: Setting condition: When the condition RTCNT =
reading out RTCSR during CMF = 1.
RTCOR is satisfied.
25
R
R
0
9
0
-
-
24
R
R
0
8
0
-
-
R/W
CMF
23
R
0
7
0
-
CMIE
R/W
22
R
0
6
0
-
R/W
21
R
0
5
0
-
CKS[2:0]
R/W
20
R
0
4
0
-
R/W
19
R
0
3
0
-
R/W
18
R
0
2
0
-
RRC[2:0]
R/W
17
R
0
1
0
-
R/W
16
R
0
0
0
-