r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 289

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

8.5
8.5.1
This LSI supports big endian, in which the 0 address is the most significant byte (MSB) in the byte
data.
Three data bus widths (8 bits, 16 bits, and 32 bits) are available for normal memory and SRAM
with byte selection. Two data bus widths (16 bits and 32 bits) are available for SDRAM. Two data
bus widths (8 bits and 16 bits) are available for PCMCIA interface. For MPX-I/O, the data bus
width is fixed at 8 bits or 16 bits, or 8 bits or 16 bits can be selected by the access address. The
data bus width for burst MPX-I/O is fixed at 32 bits. Data alignment is performed in accordance
with the data bus width of the device. This also means that when longword data is read from a
byte-width device, the read operation must be done four times. In this LSI, data alignment and
conversion of data length is performed automatically between the respective interfaces.
Tables 8.5 to 8.7 show the relationship between device data width and access unit.
Table 8.5
Operation
Byte access
at 0
Byte access
at 1
Byte access
at 2
Byte access
at 3
Word access
at 0
Word access
at 2
Longword
access at 0
Operation
Endian/Access Size and Data Alignment
32-Bit External Device Access and Data Alignment
D31 to
D24
Data
7 to 0



Data
15 to 8

Data
31 to 24
D23 to
D16

Data
7 to 0


Data
7 to 0

Data
23 to 16
Data Bus
D15 to
D8


Data
7 to 0


Data
15 to 8
Data
15 to 8
D7 to D0



Data
7 to 0

Data
7 to 0
Data
7 to 0
WE3,
DQMUU
Assert



Assert

Assert
Rev. 2.00 Dec. 09, 2005 Page 265 of 1152
Section 8 Bus State Controller (BSC)
WE2,
DQMUL

Assert


Assert

Assert
Strobe Signals
WE1,
DQMLU


Assert


Assert
Assert
REJ09B0191-0200
WE0,
DQMLL



Assert

Assert
Assert