r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 220

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 7 Cache
Rev. 2.00 Dec. 09, 2005 Page 196 of 1152
REJ09B0191-0200
1. Instruction cache
1.1 Address array access
(a) Address specification
(b) Data specification (both read and write accesses)
1.2 Data array access (both read and write accesses)
(a) Address specification
(b) Data specification
[Legend]
*:
E:
X:
Read access
111100000
Write access
111100000
111100010
31
31
31
31
31
0 0 0
Don't care
Bit 10 of entry address for read, don't care for write
0 for read, don't care for write
29 28
Figure 7.4 Specifying Address and Data for Memory-Mapped Cache Access
Tag address (28 to 11)
23 22
23 22
23 22
*----------*
*----------*
*----------*
13 12 11
13 12 11 10
13 12 11 10
Longword data
W
W
W
11 10 9
10
E
Entry address
Entry address
Entry address
LRU
4
4
4
4
0
A
3
3
3
X
3
L
X
2
*
2
*
2
2
0
0
X
0
1
1
1
1
V
0
0
0
0
0
0
0
0
2. Operand cache
2.1 Address array access
(a) Address specification
(b) Data specification (both read and write accesses)
2.2 Data array access (both read and write accesses)
(a) Address specification
(b) Data specification
Read access
Write access
111100001
111100001
111100011
31
31
31
31
31
0 0 0
29 28
Tag address (28 to 11)
23 22
23 22
23 22
*----------*
*----------*
*----------*
13 12 11
13 12 11 10
13 12 11 10
W
W
W
11 10 9
Longword data
10
E
Entry address
Entry address
Entry address
LRU
4
4
4
4
0
A
3
3
3
X
3
L
2
*
2
*
2
X
2
U
1
0
1
0
1
1
0
V
0
0
0
0
0
0
0
0