r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 746

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 15 Serial Communication Interface with FIFO (SCIF)
• Four types of interrupts: Transmit-FIFO-data-empty interrupt, break interrupt, receive-FIFO-
• When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving
• In asynchronous mode, on-chip modem control functions (RTS and CTS) (only channel 3).
• The quantity of data in the transmit and receive FIFO data registers and the number of receive
• A time-out error (DR) can be detected when receiving in asynchronous mode.
Figure 15.1 shows a block diagram of the SCIF.
Rev. 2.00 Dec. 09, 2005 Page 722 of 1152
REJ09B0191-0200
CTS
TxD
SCK
RTS
[Legend]
SCRSR:
SCFRDR:
SCTSR:
SCFTDR:
SCSMR:
SCSCR:
RxD
data-full interrupt, and receive-error interrupts are requested independently.
power.
errors of the receive data in the receive FIFO data register can be ascertained.
Receive shift register
Receive FIFO data register
Transmit shift register
Transmit FIFO data register
Serial mode register
Serial control register
SCFRDR (16 stage)
SCRSR
Parity check
SCFTDR (16 stage)
Figure 15.1 Block Diagram of SCIF
Parity generation
SCTSR
SCFSR:
SCBRR:
SCSPTR:
SCFCR:
SCFDR:
SCLSR:
Module data bus
Serial status register
Bit rate register
Serial port register
FIFO control register
FIFO data count set register
Line status register
Transmission/reception
control
SCSPTR
SCSMR
SCFDR
SCFCR
SCFSR
SCSCR
SCLSR
External clock
Clock
Baud rate
generator
SCIF
SCBRR
P φ
P φ /4
P φ /16
P φ /64
TXI
RXI
ERI
BRI
Peripheral
bus