r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 844

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 16 I
Rev. 2.00 Dec. 09, 2005 Page 820 of 1152
REJ09B0191-0200
No
No
No
Clear ACKBT in ICIER to 0
Clear RCVD in ICCR1 to 0
Set ACKBT in ICIER to 1
Clear MST in ICCR1 to 0
Clear TRS in ICCR1 to 0
Set RCVD in ICCR1 to 1
Master receive mode
2
Clear TEND in ICSR
Clear TDRE in ICSR
Dummy-read ICDRR
Read RDRF in ICSR
Read RDRF in ICSR
Read STOP in ICSR
Clear STOP in ICSR
C Bus Interface 3 (IIC3)
Write 0 to BBSY
Read ICDRR
Read ICDRR
Read ICDRR
Last receive
RDRF=1 ?
RDRF=1 ?
STOP=1 ?
and SCP
- 1?
End
Figure 16.19 Sample Flowchart for Master Receive Mode
Yes
Yes
Yes
No
Yes
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Clear the STOP flag.
[11] Issue the stop condition.
[12] Wait for the creation of stop condition.
[13] Read the last byte of receive data.
[14] Clear RCVD.
[15] Set slave receive mode.
Notes: * Make sure that no interrupt will be generated during steps [1] to [3].
Clear TEND, select master receive mode, and then clear TDRE. *
Set acknowledge to the transmit device. *
Dummy-read ICDDR. *
Wait for 1 byte to be received
Check whether it is the (last receive - 1).
Read the receive data.
Set acknowledge of the final byte. Disable continuous reception (RCVD = 1).
Read the (final byte - 1) of received data.
Wait for the last byte to be receive.
The step [8] is dummy-read in ICDRR.
When the size of receive data is only one byte in reception,
steps [2] to [6] are skipped after step [1], before jumping to step [7].