r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 724

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 13 Compare Match Timer (CMT)
13.4
13.4.1
The CMT has channels and each of them to which a different vector address is allocated has a
compare match interrupt. When both the compare match flag (CMF) and the interrupt enable bit
(CMIE) are set to 1, the corresponding interrupt request is output. When the interrupt is used to
activate a CPU interrupt, the priority of channels can be changed by the interrupt controller
settings. For details, see section 5, Interrupt Controller (INTC).
Clear the CMF bit to 0 by the user exception handling routine. If this operation is not carried out,
another interrupt will be generated. The direct memory access controller (DMAC) can be set to be
activated when a compare match interrupt is requested. In this case, an interrupt is not issued to
the CPU. If the setting to activate the DMAC has not been made, an interrupt request is sent to the
CPU. The CMF bit is automatically cleared to 0 when data is transferred by the DMAC.
13.4.2
When CMCOR and CMCNT match, a compare match signal is generated at the last state in which
the values match (the timing when the CMCNT value is updated to H'0000) and the CMF bit in
CMCSR is set to 1. That is, after a match between CMCOR and CMCNT, the compare match
signal is not generated until the next CMCNT counter clock input. Figure 13.4 shows the timing of
CMF bit setting.
Rev. 2.00 Dec. 09, 2005 Page 700 of 1152
REJ09B0191-0200
Interrupts
Interrupt Sources and DMA Transfer Requests
Timing of Compare Match Flag Setting