r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 1021
r5s72060w200fpv
Manufacturer Part Number
r5s72060w200fpv
Description
32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5S72060W200FPV.pdf
(1180 pages)
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This section gives information on the on-chip I/O registers of this LSI in the following structures.
1. Register Addresses (by functional module, in order of the corresponding section numbers)
• Registers are described by functional module, in order of the corresponding section numbers.
• Access to reserved addresses which are not described in this register address list is prohibited.
• When registers consist of 16 or 32 bits, the addresses of the MSBs are given when big-endian
2. Register Bits
• Bit configurations of the registers are described in the same order as the Register Addresses
• Reserved bits are indicated by — in the bit name.
• No entry in the bit-name column indicates that the whole register is allocated as a counter or
3. Register States in Each Operating Mode
• Register states are described in the same order as the Register Addresses (by functional
• For the initial state of each bit, refer to the description of the register in the corresponding
• The register states described are for the basic operating modes. If there is a specific reset for an
4. Notes when Writing to the On-Chip Peripheral Modules
• To access an on-chip module register, two or more peripheral module clock (Pf) cycles are
mode is selected.
(by functional module, in order of the corresponding section numbers).
for holding data.
module, in order of the corresponding section numbers).
section.
on-chip peripheral module, refer to the section on that on-chip peripheral module.
required. Care must be taken in system design. When the CPU writes data to the internal
peripheral registers, the CPU performs the succeeding instructions without waiting for the
completion of writing to registers. For example, a case is described here in which the system is
transferring to the software standby mode for power savings. To make this transition, the
SLEEP instruction must be performed after setting the STBY bit in the STBCR register to 1.
However a dummy read of the STBCR register is required before executing the SLEEP
instruction. If a dummy read is omitted, the CPU executes the SLEEP instruction before the
STBY bit is set to 1, thus the system enters sleep mode not software standby mode. A dummy
read of the STBCR register is indispensable to complete writing to the STBY bit. To reflect the
change by internal peripheral registers while performing the succeeding instructions, execute a
dummy read of registers to which write instruction is given and then perform the succeeding
instructions.
Section 24 List of Registers
Rev. 2.00 Dec. 09, 2005 Page 997 of 1152
Section 24 List of Registers
REJ09B0191-0200
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