r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 185

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

6.3.1
BAR is a 32-bit readable/writable register. BAR specifies the address used as a break condition in
each channel. The control bits CD[1:0] in the break bus cycle register (BBR) select one of the
three address buses for a break condition. BAR is initialized to H'00000000 by a power-on reset,
but retains its previous value by a manual reset or in software standby mode or sleep mode.
Note: When setting the instruction fetch cycle as a break condition, clear the LSB in BAR to 0.
Bit
31 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Break Address Register (BAR)
Bit Name
BA31 to BA0 All 0
BA31
BA15
R/W
R/W
31
15
0
0
BA30
BA14
R/W
R/W
30
14
0
0
BA29
BA13
R/W
R/W
29
13
0
0
Initial
Value
BA28
BA12
R/W
R/W
28
12
0
0
BA27
BA11
R/W
R/W
27
11
0
0
R/W
R/W
BA26
BA10
R/W
R/W
26
10
0
0
Description
Break Address
Store an address on the CPU address bus (FAB or
MAB) or IAB specifying break conditions.
When the C bus and instruction fetch cycle are
selected by BBR, specify an FAB address in bits BA31
to BA0.
When the C bus and data access cycle are selected by
BBR, specify an MAB address in bits BA31 to BA0.
BA25
R/W
R/W
BA9
25
0
9
0
BA24
R/W
R/W
BA8
24
0
8
0
BA23
R/W
R/W
BA7
23
0
7
0
Rev. 2.00 Dec. 09, 2005 Page 161 of 1152
BA22
R/W
R/W
BA6
22
0
6
0
Section 6 User Break Controller (UBC)
BA21
R/W
R/W
BA5
21
0
5
0
BA20
R/W
R/W
BA4
20
0
4
0
BA19
R/W
R/W
BA3
19
0
3
0
REJ09B0191-0200
BA18
R/W
R/W
BA2
18
0
2
0
BA17
R/W
R/W
BA1
17
0
1
0
BA16
R/W
R/W
BA0
16
0
0
0