r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 380

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 8 Bus State Controller (BSC)
8.6
8.6.1
When the burst ROM interface (clocked asynchronous) is used and the following three conditions
are met, read/write access from the external bus space immediately after write access may be
invalid.
1. The 16-bit bus width is used for the burst ROM interface (clocked asynchronous). (The
2. The burst length is specified as 4. (The CSnWCR.BST[1:0] setting is B'10)
3. Write-back is performed with operand cache or 16-byte write access is performed with the
8.6.2
When the following two conditions are met in the PCMCIA I/O card interface, read/write access
may be performed with the 8-bit bus width even if the 16-bit bus width has been specified.
1. The 16-bit bus width is specified for the PCMCIA I/O card interface (The
2. The number of delay cycles from address output to RD/WE assertion is specified as other than
8.6.3
When a contention occurs between SDRAM auto-refreshing and read/write access to the burst
MPX-I/O interface, both the CS signal of the SDRAM space and the CS signal of the burst MPX-
I/O space are asserted and access to the burst MPX-I/O may not be performed correctly.
Do not use the SDRAM interface and the burst MPX-I/O interface at the same time. Each can be
used independently, and SDRAM can be used with interfaces other than the burst MPX-I/O.
Rev. 2.00 Dec. 09, 2005 Page 356 of 1152
REJ09B0191-0200
CSnBCR.TYPE[2:0] setting is B'001 and the CSnWCR.BSZ[1:0] setting is B'10)
DMAC for the burst ROM interface set as above.
CSnBCR.TYPE[2:0] setting is B'101, the CSnBCR.BSZ[1:0] setting is B'10, and the
CSnWCR.SA[1:0] setting is not B'00)
0.5 cycle (The CSnWCR.TED[3:0] setting is not B'0000)
Usage Notes
Burst ROM Interface
PCMCIA I/O Card Interface
Burst MPX-I/O Interface