r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 1157

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Item
8.5.7 Burst ROM (Clocked
Asynchronous) Interface
Table 8.17 Relationship between
Bus Width, Access Size, and
Number of Bursts
8.5.9 PCMCIA Interface
(2) Basic Timing for I/O Card
Interface
8.5.14 Others
(2) Access from the Side of the
LSI Internal Bus Master
8.6 Usage Notes
Page Revision (See Manual for Details)
324
324
336
353,
354
356
Added.
In the single access or write access that does not
perform the burst operation in the burst ROM (clocked
asynchronous) interface, access timing is same as a
normal space. In addition, there are some restrictions
on 16-byte write access. For details, see section 8.6,
Usage Notes.
Amended.
Added.
Note that the bus width cannot be switched dynamically
with the IOIS16 signal, which is output from an I/O
card. The bus width must always be switched by
modifying the CS5BCR or CS6BCR setting. In addition,
there are some restrictions on the bus width of the I/O
card interface. For details, see section 8.6, Usage
Notes.
Amended.
cache bus → CPU bus
Added.
Bus Width
8 bits
Rev. 2.00 Dec. 09, 2005 Page 1133 of 1152
Access Size
16 bytes
CSnWCR. BST[1:0]
Bits
00
REJ09B0191-0200