r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 423

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

• Intermittent Mode 16 and Intermittent Mode 64
In intermittent mode of cycle steal, DMAC returns the bus mastership to other bus master
whenever a unit of transfer (byte, word, longword, or 16 bytes) is completed. If the next
transfer request occurs after that, DMAC obtains the bus mastership from other bus master
after waiting for 16 or 64 cycles of Bφ clock. DMAC then transfers data of one unit and returns
the bus mastership to other bus master. These operations are repeated until the transfer end
condition is satisfied. It is thus possible to make lower the ratio of bus occupation by DMA
transfer than the normal mode of cycle steal.
When DMAC obtains again the bus mastership, DMA transfer may be postponed in case of
entry updating due to cache miss.
The cycle-steal intermittent mode can be used for any transfer section; transfer request source,
transfer source, and transfer destination. The bus modes, however, must be cycle steal mode in
all channels.
Figure 9.10 shows an example of DMA transfer timing in cycle-steal intermittent mode.
Transfer conditions shown in the figure are;
 Dual address mode
 DREQ low level detection
Figure 9.10 Example of DMA Transfer in Cycle-Steal Intermittent Mode
Bus cycle
Bus cycle
DREQ
Figure 9.9 DMA Transfer Example in Cycle-Steal Normal Mode
DREQ
CPU
CPU
(Dual Address, DREQ Low Level Detection)
(Dual Address, DREQ Low Level Detection)
CPU
CPU
CPU DMAC DMAC CPU
CPU DMAC DMAC CPU
Read/Write
Bus mastership returned to CPU once
Read/Write
More than 16 or 64 Bφ clock cycles
(depends on the CPU's condition of using bus)
Section 9 Direct Memory Access Controller (DMAC)
Rev. 2.00 Dec. 09, 2005 Page 399 of 1152
DMAC DMAC CPU
CPU DMAC DMAC CPU
Read/Write
Read/Write
REJ09B0191-0200