r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 429

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Figure 9.17 shows the TEND output timing.
The unit of the DMA transfer is divided into multiple bus cycles when 16-byte transfer is
performed for an 8-bit, 16-bit, or 32-bit external device, when longword access is performed for an
8-bit or 16-bit external device, or when word access is performed for an 8-bit external device.
When a setting is made so that the DMA transfer size is divided into multiple bus cycles and the
CS signal is negated between bus cycles, note that DACK and TEND are divided like the CS
signal for data alignment as shown in figure 9.18. Also, the DREQ sampling may not be detected
correctly with divided DACK, and one extra overrun may occur at maximum. Use a setting that
does not divide DACK or specify a transfer size smaller than the external device bus width if
DACK is divided.
CKIO
Bus cycle
DREQ
DACK
TEND
Figure 9.17 Example of DMA Transfer End Signal Timing
DMAC
(Cycle Steal Mode Level Detection)
CPU
End of DMA transfer
Section 9 Direct Memory Access Controller (DMAC)
DMAC
Rev. 2.00 Dec. 09, 2005 Page 405 of 1152
CPU
CPU
REJ09B0191-0200