r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 187

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

6.3.3
BDR is a 32-bit readable/writable register. The control bits CD[1:0]in the break bus cycle register
(BBR) select one of the two data buses for a break condition. BDR is initialized to H'00000000 by
a power-on reset, but retains its previous value by a manual reset or in software standby mode or
sleep mode.
Notes: 1. Set the operand size when specifying a value on a data bus as the break condition.
Bit
31 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
2. When the byte size is selected as a break condition, the same byte data must be set in
Break Data Register (BDR)
Bit Name
BD31 to BD0 All 0
BD31
BD15
bits 31 to 24, 23 to 16, 15 to 8, and 7 to 0 in BDR as the break data. Similarly, when the
word size is selected, the same word data must be set in bits 31 to 16 and 15 to 0.
R/W
R/W
31
15
0
0
BD30
BD14
R/W
R/W
30
14
0
0
BD29
BD13
R/W
R/W
29
13
0
0
Initial
Value
BD28
BD12
R/W
R/W
28
12
0
0
BD27
BD11
R/W
R/W
27
11
0
0
R/W
R/W
BD26
BD10
R/W
R/W
26
10
0
0
Description
Break Data Bits
Store data which specifies a break condition.
If the I bus is selected in BBR, specify the break data
on IDB in bits BD31 to BD0.
If the C bus is selected in BBR, specify the break data
on MDB is set in bits BD31 to BD0.
BD25
R/W
R/W
BD9
25
0
9
0
BD24
R/W
R/W
BD8
24
0
8
0
BD23
R/W
R/W
BD7
23
0
7
0
Rev. 2.00 Dec. 09, 2005 Page 163 of 1152
BD22
R/W
R/W
BD6
22
0
6
0
Section 6 User Break Controller (UBC)
BD21
R/W
R/W
BD5
21
0
5
0
BD20
R/W
R/W
BD4
20
0
4
0
BD19
R/W
R/W
BD3
19
0
3
0
REJ09B0191-0200
BD18
R/W
R/W
BD2
18
0
2
0
BD17
R/W
R/W
BD1
17
0
1
0
BD16
R/W
R/W
BD0
16
0
0
0