r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 299

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

8.5.4
The number of cycles from CSn assertion to RD, WEn assertion can be specified by setting bits
SW1 and SW0 in CSnWCR. The number of cycles from RD, WEn negation to CSn negation can
be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device
can be obtained. Figure 8.11 shows an example. A Th cycle and a Tf cycle are added before and
after an ordinary cycle, respectively. In these cycles, RD and WEn are not asserted, while other
signals are asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful
for devices with slow writing operations.
CSn Assert Period Expansion
Write
Read
Figure 8.11 CSn Assert Period Expansion
D31 to D0
D31 to D0
A25 to A0
DACKn*
RD/WR
CKIO
Note: * The waveform for DACKn is when active low is specified.
WEn
CSn
RD
BS
Th
T1
Rev. 2.00 Dec. 09, 2005 Page 275 of 1152
T2
Section 8 Bus State Controller (BSC)
Tf
REJ09B0191-0200