r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 422

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 9 Direct Memory Access Controller (DMAC)
(2)
There are two bus modes; cycle steal and burst. Select the mode by the TB bits in the channel
control registers (CHCR).
(a)
• Normal mode
Rev. 2.00 Dec. 09, 2005 Page 398 of 1152
REJ09B0191-0200
In normal mode of cycle steal, the bus mastership is given to another bus master after a one-
transfer-unit (byte, word, longword, or 16-byte unit) DMA transfer. When another transfer
request occurs, the bus mastership is obtained from another bus master and a transfer is
performed for one transfer unit. When that transfer ends, the bus mastership is passed to
another bus master. This is repeated until the transfer end conditions are satisfied.
The cycle-steal normal mode can be used for any transfer section; transfer request source,
transfer source, and transfer destination.
Figure 9.9 shows an example of DMA transfer timing in cycle-steal normal mode. Transfer
conditions shown in the figure are;
 Dual address mode
 DREQ low level detection
Bus Modes
Cycle Steal Mode
D31 to D0
D31 to D0
A25 to A0
A25 to A0
Figure 9.8 Example of DMA Transfer Timing in Single Address Mode
DACKn
DACKn
WEn
CSn
CSn
RD
CK
CK
(b) External memory space (normal memory) → External device with DACK
(a) External device with DACK → External memory space (normal memory)
Address output to external memory space
Select signal to external memory space
Write strobe signal to external memory space
Data output from external device with DACK
DACK signal (active-low) to external device with DACK
Address output to external memory space
Select signal to external memory space
Read strobe signal to external memory space
Data output from external memory space
DACK signal (active-low) to external device with DACK