r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 787

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Figure 15.3 shows a sample flowchart for initializing the SCIF.
After reading ER, DR, and BRK flags in SCFSR,
SCFCR, and clear TFRST and RFRST bits to 0
(leaving TIE, RIE, TE, and RE bits cleared to 0)
and each flag in SCLSR, write 0 to clear them
Set RTRG[1:0], TTRG[1:0], and MCE bits in
Set TFRST and RFRST bits in SCFCR to 1
Clear TE and RE bits in SCSCR to 0
Set TE and RE bits in SCSCR to 1,
Set data transfer format in SCSMR
PFC setting for external pins used
and set TIE, RIE, and REIE bits
Set CKE[1:0] in SCSCR
Figure 15.3 Sample Flowchart for SCIF Initialization
Set value in SCBRR
Start of initialization
End of initialization
SCK, TxD, RxD
Section 15 Serial Communication Interface with FIFO (SCIF)
[1]
[2]
[3]
[4]
[5]
[1]
[2]
[3]
[4]
[5]
Set the clock selection in SCSCR.
Be sure to clear bits TIE, RIE, TE,
and RE to 0.
Set the data transfer format in
SCSMR.
Write a value corresponding to the
bit rate into SCBRR. (Not
necessary if an external clock is
used.)
Sets PFC for external pins used.
Set as RxD input at receiving and
TxD at transmission.
However, no setting for SCK pin is
required when CKE[1:0] is 00.
In the case when internal synchronous
clock output is set, the SCK pin starts
outputting the clock at this stage.
Set the TE bit or RE bit in SCSCR
to 1. Also set the RIE, REIE, and
TIE bits. Setting the TE and RE bits
enables the TxD and RxD pins to be
used.
When transmitting, the SCIF will go
to the mark state; when receiving,
it will go to the idle state, waiting for
a start bit.
Rev. 2.00 Dec. 09, 2005 Page 763 of 1152
REJ09B0191-0200