r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 72

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 2 CPU
Note:
Rev. 2.00 Dec. 09, 2005 Page 48 of 1152
REJ09B0191-0200
Instruction Formats
i format
15
ni format
15
ni3 format
15
ni20 format
32
15
nid format
32
15
xxxx
iiii
xxxx
xxxx
xxxx
xxxx
xxxx
*
nnnn
iiii
nnnn
dddd
nnnn
xxxx
xxxx
In multiply-and-accumulate instructions, nnnn is the source register.
iiii xxxx
iiii iiii
xiii xxxx
dddd dddd
nnnn
iiii
iiii
x
iiii
iiii
iii
16
16
0
0
0
0
0
Source
Operand
iiiiiiii: Immediate
iiiiiiii: Immediate
iiiiiiii: Immediate
iiiiiiii: Immediate
nnnn: Register direct
iii: Immediate
—
iiiiiiiiiiiiiiiiiiii:
Immediate
nnnndddddddddddd:
Register indirect with
displacement
iii: Immediate
—
Destination
Operand
Indexed GBR
indirect
R0 (Register direct)
—
nnnn: Register direct ADD
—
nnnn: Register direct
iii: Immediate
nnnn: Register direct MOVI20
—
nnnndddddddddddd:
Register indirect with
displacement
iii: Immediate
BLD
BST
#imm20, Rn
BLD.B
#imm3,@(disp12,Rn
)
BST.B
#imm3,@(disp12,Rn
)
Example
AND.B
#imm,@(R0,GBR)
AND
TRAPA
#imm3,Rn
#imm3,Rn
#imm,R0
#imm
#imm,Rn