r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 103
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r5s72060w200fpv
Manufacturer Part Number
r5s72060w200fpv
Description
32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5S72060W200FPV.pdf
(1180 pages)
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3.4.1
FRQCR is a 16-bit readable/writable register used to specify whether a clock is output from the
CKIO pin in software standby mode, the frequency multiplication ratio of PLL circuit 1, and the
frequency division ratio of the internal clock and peripheral clock (Pφ). Only word access can be
used on FRQCR.
FRQCR is initialized to H'1003 only by a power-on reset. FRQCR retains its previous value by a
manual reset or in software standby mode. The previous value is also retained when an internal
reset is triggered by an overflow of the WDT.
Initial value:
Bit
15 to 13
12
R/W:
Bit:
Frequency Control Register (FRQCR)
Bit Name
CKOEN
15
R
0
-
14
R
0
-
13
R
0
-
Initial
Value
All 0
1
CKOEN
R/W
12
1
11
R
0
-
R/W
R
R/W
R/W
10
0
STC[2:0]
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Clock Output Enable
Specifies whether a clock is output from the CKIO pin,
or whether the CKIO pin is placed in the level-fixed
state during standby mode or cancellation of standby
mode.
If this bit is cleared to 0, the CKIO pin is fixed at low
during standby mode or cancellation of standby
mode. Therefore, the malfunction of an external circuit
because of an unstable CKIO clock during
cancellation of standby mode can be prevented. In
clock operating mode 7, the CKIO pin functions as an
input regardless of this bit value.
0: The CKIO pin is fixed to the low level during
1: Clock is output from CKIO pin (placed in the high-
R/W
9
0
standby mode or cancellation of standby mode.
(Clock is output during the period other than
standby mode or cancellation of standby mode.)
impedance state during standby mode).
R/W
8
0
R
7
0
-
Rev. 2.00 Dec. 09, 2005 Page 79 of 1152
Section 3 Clock Pulse Generator (CPG)
R/W
6
0
IFC[2:0]
R/W
5
0
R/W
4
0
RNGS
R/W
3
0
REJ09B0191-0200
R/W
2
0
PFC[2:0]
R/W
1
1
R/W
0
1
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