r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 149

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

5.3.9
IBNR is a 16-bit register that enables or disables use of register banks and register bank overflow
exception. IBNR also indicates the bank number to which saving is performed next through the
bits BN3 to BN0.
IBNR is initialized to H'0000 by a power-on reset.
Initial value:
Bit
15, 14
13
12 to 4
R/W:
Bit:
Bank Number Register (IBNR)
Bit Name
BE[1:0]
BOVE

R/W
15
0
BE[1:0]
R/W
14
0
BOVE
R/W
13
0
Initial
Value
00
0
All 0
12
R
0
-
11
R
0
-
R/W
R/W
R/W
R
10
R
0
-
Description
Register Bank Enable
These bits enable or disable use of register banks.
00: Use of register banks is disabled for all interrupts.
01: Use of register banks is enabled for all interrupts
10: Reserved (setting prohibited)
11: Use of register banks is controlled by the setting of
Register Bank Overflow Enable
Enables of disables register bank overflow exception.
0: Generation of register bank overflow exception is
1: Generation of register bank overflow exception is
Reserved
These bits are always read as 0. The write value should
always be 0.
disabled
enabled
R
The setting of IBCR is ignored.
except NMI and user break. The setting of IBCR is
ignored.
IBCR.
9
0
-
R
8
0
-
R
7
0
-
Rev. 2.00 Dec. 09, 2005 Page 125 of 1152
R
6
0
-
Section 5 Interrupt Controller (INTC)
R
5
0
-
R
4
0
-
R
3
0
REJ09B0191-0200
R
2
0
BN[3:0]
R
1
0
R
0
0