r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 129

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

4.6.5
When an integer division instruction performs division by zero or the result of integer division
overflows, integer division instruction exception handling starts. The instructions that may become
the source of division-by-zero exception are DIVU and DIVS. The only source instruction of
overflow exception is DIVS, and overflow exception occurs only when the negative maximum
value is divided by −1. The CPU operates as follows:
1. The exception service routine start address which corresponds to the integer division
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
4. After jumping to the exception service routine start address fetched from the exception
instruction exception that occurred is fetched from the exception handling vector table.
integer division instruction at which the exception occurred.
handling vector table, program execution starts. The jump that occurs is not a delayed branch.
Integer Division Instructions
Rev. 2.00 Dec. 09, 2005 Page 105 of 1152
Section 4 Exception Handling
REJ09B0191-0200