r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 825

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

16.3.6
SAR is an 8-bit readable/writable register that selects the communications format and sets the
slave address. In slave mode with the I
upper seven bits of the first frame received after a start condition, this module operates as the slave
device.
SAR is initialized to H'00 by a power-on reset.
16.3.7
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to
ICDRS and starts transferring data. If the next transfer data is written to ICDRT during
transferring data of ICDRS, continuous transfer is possible. ICDRT is initialized to H'FF.
Bit
7 to 1
0
Slave Address Register (SAR)
I
2
Bit Name
SVA[6:0]
FS
C Bus Transmit Data Register (ICDRT)
Initial value:
Initial value:
R/W:
R/W:
Initial
Value
0000000
0
Bit:
Bit:
R/W
R/W
7
0
7
1
R/W
R/W
R/W
R/W
R/W
2
C bus format, if the upper seven bits of SAR match the
6
0
6
1
R/W
R/W
5
0
5
1
Description
Slave Address
These bits set a unique address in these bits,
differing form the addresses of other slave devices
connected to the I
Format Select
0: I
1: Clocked synchronous serial format is selected
SVA[6:0]
R/W
2
R/W
C bus format is selected
4
0
4
1
R/W
R/W
3
0
3
1
Rev. 2.00 Dec. 09, 2005 Page 801 of 1152
R/W
R/W
2
0
2
1
2
C bus.
Section 16 I
R/W
R/W
1
0
1
1
R/W
R/W
FS
0
0
0
1
2
C Bus Interface 3 (IIC3)
REJ09B0191-0200