mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 978

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map/Register Definitions
Addresses: FFFF_9000h base + C0h offset + (4d × n), where n = 0d to 15d
39.4.24 USB Control Register (USBx_USBCTRL)
Addresses: USB0_USBCTRL is FFFF_9000h base + 100h offset = FFFF_9100h
978
HOSTWOHUB
RETRYDIS
EPCTLDIS
EPSTALL
Reserved
EPRXEN
EPHSHK
EPTXEN
Reset
Field
Reset
Read
Read
Write
Write
7
6
5
4
3
2
1
0
Bit
Bit
HOSTWOHUB
SUSP
This is a Host mode only bit and is only present in the control register for endpoint 0 (ENDPT0). When set
this bit allows the host to communicate to a directly connected low speed device. When cleared, the host
produces the PRE_PID then switch to low speed signaling when sending a token to a low speed device
as required to communicate with a low speed device through a hub.
This is a Host mode only bit and is only present in the control register for endpoint 0 (ENDPT0). When set
this bit causes the host to not retry NAK'ed (Negative Acknowledgement) transactions. When a
transaction is NAKed, the BDT PID field is updated with the NAK PID, and the TOKEN_DNE interrupt is
set. When this bit is cleared NAKed transactions is retried in hardware. This bit must be set when the host
is attempting to poll an interrupt endpoint.
This read-only bit is reserved and always has the value zero.
This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This
applies if and only if the EPRXEN and EPTXEN bits are also set.
This bit, when set, enables the endpoint for RX transfers.
This bit, when set, enables the endpoint for TX transfers.
When set this bit indicates that the endpoint is called. This bit has priority over all other control bits in the
EndPoint Enable Register, but it is only valid if EPTXEN=1 or EPRXEN=1. Any access to this endpoint
causes the USB Module to return a STALL handshake. After an endpoint is stalled it requires intervention
from the Host Controller.
When set this bet enables an endpoint to perform handshaking during a transaction to this endpoint. This
bit is generally set unless the endpoint is Isochronous.
7
0
7
1
RETRYDIS
PDE
0
1
6
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
USBx_ENDPTn field descriptions
0
0
0
5
5
Preliminary
EPCTLDIS
0
0
4
4
Description
EPRXEN
0
0
3
3
0
EPTXEN
0
0
2
2
Freescale Semiconductor, Inc.
EPSTALL
0
0
1
1
EPHSHK
0
0
0
0