mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 133

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mcf51jf128

Manufacturer Part Number
mcf51jf128
Description
Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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3.10.5.3 I
The I
receive. The following table shows the TCR2[CLKMODE] settings for SAI in this MCU.
MCLK Input Clock Select bit of MCLK Control Register (MCR[MICS]) selects the
clock input to the MCLK Divider. The following table shows the options for the input
clock to the I2S/SAI module’s MCLK divider.
3.11
3.11.1 Rapid GPIO (RGPIO) Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Freescale Semiconductor, Inc.
00
01
10
11
00
01
10
11
2
S/SAI only supports one audio master clock in master mode for both transmit and
Human-machine interfaces (HMI)
2
S/SAI Clocking
TCR2[CLKMODE]
MCR[MICS]
Table 3-53. I
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Table 3-54. MCLK input clock selection
2
S/SAI master clock setting
Preliminary
Bus Clock
SAI_MCLK
Not supported
Not supported
System Clock
ERCLK1
ERCLK2
MCGPLLOUT
Clock Selection
Master Clock
Chapter 3 Chip Configuration
133

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