mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 640

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Register Definition
640
ADLSMP
ADICLK
ADLPC
MODE
ADIV
Field
6–5
3–2
1–0
7
4
Low-power configuration
ADLPC controls the power configuration of the successive approximation converter. This optimizes power
consumption when higher sample rates are not required.
0
1
Clock divide select
ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK.
00
01
10
11
Sample time configuration
ADLSMP selects between different sample times based on the conversion mode selected. This bit adjusts
the sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion
speed for lower impedance inputs. Longer sample times can also be used to lower overall power
consumption if continuous conversions are enabled and high conversion rates are not required. When
ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the extent of the long sample
time.
0
1
Conversion mode selection
MODE bits are used to select the ADC resolution mode.
00
01
10
11
Input clock select
ADICLK bits select the input clock source to generate the internal clock, ADCK. Note that when the
ADACK clock source is selected, it is not required to be active prior to conversion start. When it is
selected and it is not active prior to a conversion start (ADACKEN=0), the asynchronous clock is activated
at the start of a conversion and shuts off when conversions are terminated. In this case, there is an
associated clock startup delay each time the clock source is re-activated.
00
01
10
11
Normal power configuration.
Low power configuration. The power is reduced at the expense of maximum clock speed.
Short sample time.
Long sample time.
The divide ratio is 1 and the clock rate is input clock.
The divide ratio is 2 and the clock rate is (input clock)/2.
The divide ratio is 4 and the clock rate is (input clock)/4.
The divide ratio is 8 and the clock rate is (input clock)/8.
It is single-ended 8-bit conversion.
It is single-ended 12-bit conversion.
It is single-ended 10-bit conversion.
Reserved. Do not set the bitfield to this value.
Bus clock.
Bus clock divided by 2.
Alternate clock (ALTCLK).
Asynchronous clock (ADACK).
ADCx_CFG1 field descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Description
Freescale Semiconductor, Inc.