mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1290

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
The following figure shows the host receiving a logic 1 from the target MCU. Because
the host is asynchronous to the target MCU, there is a 0–1 cycle delay from the host-
generated falling edge on BKGD to the perceived start of the bit time in the target MCU.
The host holds the BKGD pin low long enough for the target to recognize it (at least two
target BDC cycles). The host must release the low drive before the target MCU drives a
brief active-high speedup pulse seven cycles after the perceived start of the bit time. The
host should sample the bit level about 10 cycles after it started the bit time.
The following figure shows the host receiving a logic 0 from the target MCU. Because
the host is asynchronous to the target MCU, there is a 0–1 cycle delay from the host-
generated falling edge on BKGD to the start of the bit time as perceived by the target
1290
PERCEIVED START
SYNCHRONIZATION
PERCEIVED START
SPEEDUP PULSE
(TARGET MCU)
(TARGET MCU)
UNCERTAINTY
TARGET MCU
TO BKGD PIN
HOST DRIVE
BDC CLOCK
OF BIT TIME
TRANSMIT 1
TRANSMIT 0
BDC CLOCK
OF BIT TIME
BKGD PIN
HOST
HOST
Figure 50-4. BDC Target-to-Host Serial Bit Timing (Logic 1)
Figure 50-3. BDC Host-to-Target Serial Bit Timing
MCF51JF128 Reference Manual, Rev. 2, 03/2011
HIGH-IMPEDANCE
R-C RISE
HOST SAMPLES BKGD PIN
10 CYCLES
TARGET SENSES BIT LEVEL
10 CYCLES
10 CYCLES
Preliminary
HIGH-IMPEDANCE
HIGH-IMPEDANCE
EARLIEST START
Freescale Semiconductor, Inc.
EARLIEST START
OF NEXT BIT
OF NEXT BIT