mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 513

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

23.4.9.1 Command Write Sequence
FTFL commands are specified using a command write sequence illustrated in
23-32. The FTFL module performs various checks on the command (FCCOB) content
and continues with command execution if all requirements are fulfilled.
Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register
must be zero and the CCIF flag must read 1 to verify that any previous command has
completed. If CCIF is zero, the previous command execution is still active, a new
command write sequence cannot be started, and all writes to the FCCOB registers are
ignored.
23.4.9.1.1 Load the FCCOB Registers
The user must load the FCCOB registers with all parameters required by the desired
FTFL command. The individual registers that make up the FCCOB data set can be
written in any order.
23.4.9.1.2 Launch the Command by Clearing CCIF
Once all relevant command parameters have been loaded, the user launches the command
by clearing the FSTAT[CCIF] bit by writing a '1' to it. The CCIF flag remains zero until
the FTFL command completes.
The FSTAT register contains a blocking mechanism, which prevents a new command
from launching (can't clear CCIF) if the previous command resulted in an access error
(FSTAT[ACCERR]=1) or a protection violation (FSTAT[FPVIOL]=1). In error
scenarios, two writes to FSTAT are required to initiate the next command: the first write
clears the error flags, the second write clears CCIF.
23.4.9.1.3 Command Execution and Error Reporting
The command processing has several steps:
Freescale Semiconductor, Inc.
1. In the first step, the FTFL reads the command code and performs a series of
parameter checks which are unique to each command.
If the initial parameter check fails, the FSTAT[ACCERR] (access error) bit is set.
ACCERR reports invalid instruction codes and out-of bounds addresses. Usually,
access errors suggest that the command was not set-up with valid parameters in the
FCCOB register group. Command processing never proceeds to execution when the
parameter checking step fails. Instead, the FSTAT[ACCERR] flag is set and the
command processing is terminated after setting CCIF.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Chapter 23 Flash Memory Module (FTFL)
Figure
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