mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 447

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

20.4.1.1 MCG Modes of Operation
The MCG operates in one of the following modes.
Freescale Semiconductor, Inc.
FLL Engaged Internal
(FEI)
Mode
The MCG restricts transitions between modes. For the
permitted transitions, see
• During exits from LLS or VLPS when the MCG is in PEE
• If entering Normal Stop mode when the MCG is in PEE
mode, the MCG will reset to PBE clock mode and the
C1[CLKS] and S[CLKST] will automatically be set to
2’b10.
mode with C5[PLLSTEN]=0, the MCG will reset to PBE
clock mode and C1[CLKS] and S[CLKST] will
automatically be set to 2’b10.
FLL engaged internal (FEI) is the default mode of operation and is entered when all the following
condtions occur:
In FEI mode, MCGOUT is derived from the FLL clock (DCOCLK) that is controlled by the 32 kHz
Internal Reference Clock (IRC). The FLL loop will lock the DCO frequency to the FLL factor, as
selected by the C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency . Refer
to the C4[DMX32] bit description for more details. In FEI mode, the PLL is disabled in a low-power
state unless C5[PLLCLKEN] is set.
Description
• C1[CLKS] bits are written to 00
• C1[IREFS] bit is written to 1
• C6[PLLS] bit is written to 0
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Table 20-14. MCG Modes of Operation
Table continues on the next page...
Figure
Preliminary
NOTE
Note
20-12.
Chapter 20 Multipurpose Clock Generator (MCG)
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