mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 885

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

37.4.21 DMA
The channel generates a DMA transfer request according to DMA and CHnIE bits (see
the following table).
If DMA = 1, the CHnF bit is cleared either by channel DMA transfer done or reading
CnSC while CHnF is set and then writing a logic 0 to CHnF bit according to CHnIE bit
(see the following table).
Freescale Semiconductor, Inc.
Notes
- FTM counter configuration: (FTMEN = 1), (QUADEN = 0) if the quadrature decoder feature is supported,
- FTM channel n configuration: input capture mode – (DECAPEN = 0), (COMBINE = 0), and (MSnB:MSnA = 0:0)
DMA
FTM counter clock
(CAPTEST = 1), (CPWMS = 0), (CNTINH:L = 0x0000), and (MODH:L = 0xFFFF)
0
0
1
1
write to MODE
write to CNTH
write to CNTL
CAPTEST bit
FTM counter
CHnIE
CH0F bit
C0VH:L
0
1
0
1
The channel DMA transfer request is not generated.
The channel DMA transfer request is not generated.
The channel DMA transfer request is not generated.
The channel DMA transfer request is generated if
(CHnF = 1).
Channel DMA Transfer Request
0x1053 0x1054 0x1055
Table 37-190. Channel DMA Transfer Request
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Figure 37-209. Capture Test Mode
set CAPTEST
0x0300
0x1056
Preliminary
write 0x78
0x7856
write 0xAC
The channel interrupt is not generated.
The channel interrupt is generated if (CHnF = 1).
The channel interrupt is not generated.
The channel interrupt is not generated.
Channel Interrupt
0x78AC
clear CAPTEST
0x78AD
Chapter 37 FlexTimer (FTM)
0x78AC
0x78AE 0x78AF 0x78B0
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