mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1166

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Data FIFO
When reading the Receive Data Register (RDR), the read FIFO pointer increments after
each valid read. The SAI supports 8-bit and 16-bit reads from RDR for receiving 8-bit
and 16-bit data respectively.
Reads from the Receive Data Register are ignored if the corresponding Receive Channel
Enable is clear or if the FIFO is empty. If the Receive FIFO is full, the Receive Data
Register must be read at least three bit clocks before the end of an unmasked word to
avoid a FIFO overrun.
44.4.6 Word mask register
The SAI transmitter and receiver each contain a word mask register that can be used to
mask any word in the frame. Since the Word Mask Register is double buffered, software
can update it before the end of each frame to mask a particular word in the next frame.
The transmitter word mask causes the Transmit Data pin to be tri-stated for the length of
each selected word and the transmit FIFO is not read for masked words.
The receiver word mask causes the received data for each selected word to be discarded
and not written to the receive FIFO.
44.4.7 Interrupts and DMA requests
The SAI transmitter and receiver generate separate interrupts and separate DMA requests,
but support the same status flags. Asynchronous versions of the transmitter and receiver
interrupts are generated to wake up the CPU from stop mode.
44.4.7.1 FIFO data ready flag
The FIFO data ready flag is set based on the number of entries in the FIFO and the FIFO
watermark configuration.
The transmit data ready flag is set when the number of entries in any of the enabled
transmit FIFOs is less than or equal to the transmit FIFO watermark configuration and is
cleared when the number of entries in each enabled transmit FIFO is greater than the
transmit FIFO watermark configuration.
The receive data ready flag is set when the number of entries in any of the enabled
receive FIFOs is greater than the receive FIFO watermark configuration and is cleared
when the number of entries in each enabled receive FIFO is less than or equal to the
receive FIFO watermark configuration.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
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Freescale Semiconductor, Inc.