mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 887

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

If the selected edge by channel (n) bits is detected at channel (n) input, then CH(n)F bit is
set and the channel (n) interrupt is generated (if CH(n)IE = 1). If the selected edge by
channel (n+1) bits is detected at channel (n) input and (CH(n)F = 1), then CH(n+1)F bit is
set and the channel (n+1) interrupt is generated (if CH(n+1)IE = 1).
The C(n)VH:L registers store the value of FTM counter when the selected edge by
channel (n) is detected at channel (n) input. The C(n+1)VH:L registers store the value of
FTM counter when the selected edge by channel (n+1) is detected at channel (n) input.
In this mode, the coherency mechanism of the pair of channels allows to access coherent
data when the C(n)VH:L and C(n+1)VH:L registers are read. The only requirement is
that C(n)VH:L registers must be read first than C(n+1)VH:L registers.
37.4.22.1 One-Shot Capture Mode
The one-shot capture mode is selected when (FTMEN = 1), (DECAPEN = 1), and
(MS(n)A = 0). In this capture mode, only one pair of edges at the channel (n) input is
captured. The ELS(n)B:ELS(n)A bits select the first edge to be captured, and ELS(n
+1)B:ELS(n+1)A bits select the second edge to be captured.
The edge captures are enabled while DECAP bit is set. For each new measurement in
one-shot capture mode, first the CH(n)F and CH(n+1) bits must be cleared, and then the
DECAP bit must be set.
In this mode, the DECAP bit is automatically cleared by FTM when the edge selected by
channel (n+1) is captured. Therefore, while DECAP bit is set, the one-shot capture is in
process. When this bit is cleared, both edges were captured and the captured values are
ready for reading in the C(n)VH:L and C(n+1)VH:L registers.
Similarly, when the CH(n+1)F bit is set, both edges were captured and the captured
values are ready for reading in the C(n)VH:L and C(n+1)VH:L registers.
Freescale Semiconductor, Inc.
• The CH(n)F, CH(n)IE, MS(n)A, ELS(n)B, and ELS(n)A
• The CH(n+1)F, CH(n+1)IE, MS(n+1)A, ELS(n+1)B, and
• It is expected that the dual edge capture mode be used with
bits are channel (n) bits.
ELS(n+1)A bits are channel (n+1) bits.
ELS(n)B:ELS(n)A = 0:1 or 1:0, ELS(n+1)B:ELS(n+1)A =
0:1 or 1:0 and the FTM counter in free running counter
mode (see
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Free Running
Preliminary
Note
Counter).
Chapter 37 FlexTimer (FTM)
887