mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1066

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Module Memory Map
43.3.4 UART Control Register 2 (UARTx_C2)
This register can be read or written at any time.
Addresses: UART0_C2 is FFFF_8140h base + 3h offset = FFFF_8143h
1066
TCIE
Field
Reset
Field
Read
Write
TIE
PT
0
7
6
Bit
UART1_C2 is FFFF_8160h base + 3h offset = FFFF_8163h
TIE
Enables the parity function. When parity is enabled, parity function inserts a parity bit in the bit position
immediately preceding the stop bit. This bit must be set when 7816E is set/enabled.
0
1
Parity Type
PT determines whether the UART generates and checks for even parity or odd parity. With even parity,
an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an
odd number of 1s clears the parity bit and an even number of 1s sets the parity bit.This bit must be
cleared when 7816E is set/enabled.
0
1
Transmitter Interrupt or DMA Transfer Enable.
TIE enables the S1[TDRE] flag, to generate interrupt requests or DMA transfer requests, based on the
state of C5[TDMAS].
NOTE: If C2[TIE] and C5[TDMAS] are both set, then TCIE must be cleared, and D[D] must not be
0
1
Transmission Complete Interrupt Enable
TCIE enables the transmission complete flag, S1[TC], to generate interrupt requests.
0
1
7
0
Parity function disabled.
Parity function enabled.
Even parity.
Odd parity.
TDRE interrupt and DMA transfer requests disabled.
TDRE interrupt or DMA transfer requests enabled.
TC interrupt requests disabled.
TC interrupt requests enabled.
written outside of servicing of a DMA request.
TCIE
UARTx_C1 field descriptions (continued)
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
UARTx_C2 field descriptions
Table continues on the next page...
RIE
0
5
Preliminary
ILIE
0
4
Description
Description
TE
0
3
RE
0
2
Freescale Semiconductor, Inc.
RWU
0
1
SBK
0
0