mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1291

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

MCU. The host initiates the bit time, but the target MCU finishes it. Because the target
wants the host to receive a logic 0, it drives the BKGD pin low for 13 BDC clock cycles,
then briefly drives it high to speed up the rising edge. The host samples the bit level about
10 cycles after starting the bit time.
50.4.1.4 BDM Command Set Descriptions
This section presents detailed descriptions of the BDM commands.
The V1 BDM command set is based on transmission of one or more 8-bit data packets
per operation. Each operation begins with a host-to-target transmission of an 8-bit
command code packet. The command code definition broadly maps the operations into
four formats as shown in the following figure.
Freescale Semiconductor, Inc.
PERCEIVED START
SPEED-UP PULSE
(TARGET MCU)
TARGET MCU
TO BKGD PIN
HOST DRIVE
BDC CLOCK
OF BIT TIME
DRIVE AND
BKGD PIN
Figure 50-5. BDM Target-to-Host Serial Bit Timing (Logic 0)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
10 CYCLES
HOST SAMPLES BKGD PIN
10 CYCLES
Preliminary
HIGH-IMPEDANCE
SPEEDUP
PULSE
EARLIEST START
OF NEXT BIT
Chapter 50 Debug
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