mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1289

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Chapter 50 Debug
When the MCU is reset in active background (halt) mode, CLKSW is set which selects
the bus clock as the source of the BDC clock. This CLKSW setting is most commonly
used during flash memory programming because the bus clock can usually be configured
to operate at the highest allowed bus frequency to ensure the fastest possible flash
programming times. Because the host system is in control of changes to clock generator
settings, it knows when a different BDC communication speed should be used. The host
programmer also knows that no unexpected change in bus frequency could occur to
disrupt BDC communications.
Normally, setting CLKSW should not be used for general debugging because there is no
way to ensure the application program does not change the clock generator settings. This
is especially true in the case of application programs that are not yet fully debugged.
After any reset (or at any other time), the host system can issue a SYNC command to
determine the speed of the BDC clock. CLKSW may be written using the serial
WRITE_XCSR_BYTE command through the BDC interface. CLKSW is located in the
special XCSR byte register in the BDC module and it is not accessible in the normal
memory map of the ColdFire core. This means that no program running on the processor
can modify this register (intentionally or unintentionally).
The BKGD pin can receive a high- or low-level or transmit a high- or low-level. The
following diagrams show timing for each of these cases. Interface timing is synchronous
to clocks in the target BDC, but asynchronous to the external host. The internal BDC
clock signal is shown for reference in counting cycles.
The following figure shows an external host transmitting a logic 1 or 0 to the BKGD pin
of a target MCU. The host is asynchronous to the target so there is a 0–1 cycle delay from
the host-generated falling edge to where the target perceives the beginning of the bit time.
Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin.
Typically, the host actively drives the pseudo-open-drain BKGD pin during host-to-target
transmissions to speed up rising edges. Because the target does not drive the BKGD pin
during the host-to-target transmission period, there is no need to treat the line as an open-
drain signal during this period.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.
1289