mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1256

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Register Descriptions
The ColdFire debug architecture supports a number of hardware breakpoint registers that
can be configured into single- or double-level triggers based on the PC or operand
address ranges with an optional inclusion of specific data values. The triggers can be
configured to halt the processor or generate a debug interrupt exception. Additionally,
these same breakpoint registers can be used to specify start/stop conditions for recording
in the PST trace buffer.
The core includes four PC breakpoint triggers and a set of operand address breakpoint
triggers with two independent address registers (to allow specification of a range) and an
optional data breakpoint with masking capabilities. Core breakpoint triggers are
accessible through the serial BDM interface or written through the supervisor
programming model using the WDEBUG instruction.
1256
DRc[4:0]
0x0C
0x0D
0x0E
0x0F
0x1A
0x1B
0x00
0x01
0x02
0x03
0x05
0x06
0x07
0x08
0x09
0x18
—
—
—
Configuration/Status Register (CSR)
Extended Configuration/Status Register (XCSR)
Configuration/Status Register 2 (CSR2)
Configuration/Status Register 3 (CSR3)
Debug Control Register (DBGCR)
Debug Status Register (DBGSR)
BDM Address Attribute Register (BAAR)
Address Attribute Trigger Register (AATR)
Trigger Definition Register (TDR)
Program Counter Breakpoint Register 0 (PBR0)
Program Counter Mask Register (PBMR)
Address Breakpoint High Register (ABHR)
Address Breakpoint Low Register (ABLR)
Data Breakpoint Register (DBR)
Data Breakpoint Mask Register (DBMR)
Program Counter Breakpoint Register 1 (PBR1)
Program Counter Breakpoint Register 2 (PBR2)
Program Counter Breakpoint Register 3 (PBR3)
PST Trace
Buffern (PSTBn); n = 0–11 (0xB)
Table 50-4. Debug Module Memory Map
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Register
Preliminary
Width
(bits)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
2
2
2
R/W
R/W
R/W
R/W (BDM), W
Indirect W via
CSR3 (BDM)
Indirect R via
CSR3 (BDM)
R (BDM)
Access
1
1
(CPU)
(CPU)
1
(CPU)
(CPU)
(BDM), W
(BDM), W
(BDM), W
W
W
W
W
W
W
W
W
W
W
W
W
3
Freescale Semiconductor, Inc.
0x0090_0000
0x0000_0000
See section
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0005
0x0000_0005
0x0000_0000
Undefined, unaffected
Undefined, unaffected
Undefined, unaffected
0x0000_0000
0x0000_0000
0x0000_0000
PBR1[0] = 0
PBR2[0] = 0
PBR3[0] = 0
Undefined, unaffected
Reset Value