mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 392

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
17.4.2.1 Stop Mode Entry Sequence
Entry to a low power stop mode (STOP, VLPS, LLS, VLLSx) is initiated by CPU
execution of the STOP instruction. After the stop instruction is executed, the following
sequence occurs:
392
1. The CPU clock is gated off immediately.
2. Requests are made to all non-CPU bus masters to enter stop mode.
3. After all masters have acknowledged they are ready to enter stop mode, requests are
4. After all slaves have acknowledged they are ready to enter stop mode, all system and
5. Clock generators are disabled in the MCG.
6. The on-chip regulator in the PMC and internal power switches are configured to
Leakage
Wakeup
System
Power
made to all bus slaves to enter stop mode.
bus clocks are gated off.
meet the power consumption goals for the targeted low power mode.
(LLWU)
Low -
(PMC)
PMC low power bus
Figure 17-6. Low power system components and connections
LP exit
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Controller
Module
System
Control
System
Clocks
Reset
Mode
(RCM)
(SMC)
(MCG)
LP exit
MCG enable
Preliminary
CCM low power bus
Module
Control
Clock
Flash
(FTFL)
CPU
(CCM)
Stop/Wait
Flash low power bus
Freescale Semiconductor, Inc.
Bus masters low power bus (non-CPU)
Bus slaves low power bus