mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 547

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mcf51jf128

Manufacturer Part Number
mcf51jf128
Description
Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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24.2.1 Address and Data Buses (FB_An, FB_Dn, FB_ADn)
In non-multiplexed mode, the FB_A[19:0] and FB_D[7:0] buses carry the address and
data, respectively.
In multiplexed mode, the FB_AD[19:0] bus carries the address and data. The full 20-bit
address is driven on the first clock of a bus cycle (address phase). Following the first
clock, the data is driven on the bus (data phase). During the data phase, the address
continues driving on the pins not used for data. For example, in 16-bit mode the lower
address continues driving on FB_AD[19:16] and in 8-bit mode the lower address
continues driving on FB_AD[19:8].
24.2.2 Chip Selects (FB_CS[ 1:0])
The chip-select signal indicates which device is selected. A particular chip-select asserts
when the transfer address is within the device's address space, as defined in the base- and
mask-address registers. The actual number of chip selects available depends upon the pin
configuration.
24.2.3 Output Enable (FB_OE)
The output enable signal (FB_OE) is sent to the interfacing memory and/or peripheral to
enable a read transfer. FB_OE is only asserted during read accesses when a chip select
matches the current address decode.
Freescale Semiconductor, Inc.
FB_CS[1:0]
FB_A[19:0]
FB_D[7:0]
FB_R/W
FB_ALE
FB_OE
FB_TS
Signal
In a non-multiplexed configuration, this is the address bus. In a
multiplexed configuration this bus is the address/data bus, FB_AD[19:0].
In a non-multiplexed configuration, this is the data bus. In multiplexed
configurations, this bus is not used.
General purpose chip-selects. The actual number of chip selects available
depends upon the device and its pin configuration.
Output enable
Read/write. 1 = Read, 0 = Write
Transfer start
Address latch enable (an inverse of FB_TS)
Description
Table 24-1. Mini-FlexBus Signal Descriptions
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Chapter 24 External Bus Interface (Mini-FlexBus)
I/O
I/O
I/O
O
O
O
O
O
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