mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1261

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
WDEBUG instruction
DRc: 0x01 (XCSR)
R
W
Reset
R
W
Reset
CPUSTOP
CPUHALT
Field
31
30
31
0
15
0
0
30
0
14
0
0
Table 50-8. Extended Configuration/Status Register (XCSR)
Reference method
CPU Halt
Indicates that the CPU is in the halt state. The CPU state may be running, stopped, or halted, as
indicated by the CPUHALT and CPUSTOP bits. If both CPUHALT and CPUSTOP are 0, then the
CPU is running.
CPU Stop
Indicates that the CPU is in the stop state. The CPU state may be running, stopped, or halted, as
indicated by the CPUHALT and CPUSTOP bits. If both CPUHALT and CPUSTOP are 0, then the
CPU is running.
Description
29
0
13
0
0
Table 50-7. XCSR Access Summary
CSTAT
MCF51JF128 Reference Manual, Rev. 2, 03/2011
28
0
12
0
0
Table 50-9. XCSR Field Descriptions
27
0
11
0
0
Table continues on the next page...
(continued)
26
0
10
0
0
CLK
SW
25
0
9
0
Preliminary
SEC
0
24
0
8
0
0
ENB
Writes bits 23–0 during execution of the core WDEBUG
instruction. This instruction is a privileged supervisor-mode
instruction.
DM
23
0
0
7
0
0
22
0
6
0
0
0
21
0
0
5
0
0
Details
20
0
4
0
0
0
Access: Supervisor write-only
19
0
3
0
0
0
18
0
0
2
0
Chapter 50 Debug
APCSC
BDM read/write
17
0
1
0
0
16
0
0
0
0
APC
ENB
1261