mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 736

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Reset
Memory Map and Register Definition
33.3.6 Channel n Status Register (PDBx_CHnS)
Addresses: PDB0_CH0S is FFFF_8540h base + 14h offset = FFFF_8554h
736
Bit
W
R
Reserved
Reserved
31
0
31–24
23–16
15–8
Field
Field
ERR
7–0
7–0
EN
CF
30
0
29
0
28
0
0
PDB Channel Pre-Trigger Enable
These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger bits are implemented in this
MCU.
0
1
This read-only bitfield is reserved and always has the value zero.
PDB Channel Flags
The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to clear these bits.
This read-only bitfield is reserved and always has the value zero.
PDB Channel Sequence Error Flags
Only the lower M bits are implemented in this MCU.
0
1
27
0
PDB channel's corresponding pre-trigger disabled.
PDB channel's corresponding pre-trigger enabled.
Sequence error not detected on PDB channel's corresponding pre-trigger.
Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered
for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by
one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's
corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1’s to clear the
sequence error flags.
26
0
25
0
24
PDBx_CHnC1 field descriptions (continued)
0
MCF51JF128 Reference Manual, Rev. 2, 03/2011
23
0
22
0
PDBx_CHnS field descriptions
21
0
20
0
CF
19
0
18
0
Preliminary
17
0
16
0
15
0
Description
Description
14
0
13
0
12
0
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
4
0
ERR
0
3
0
2
0
1
0
0