mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1205

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

46.4.4 Digital filters
The passive input low-pass filter can filter only signals greater than 10 MHz . EGPIO
provides programmable digital filters to filter signals much less than 10 MHz for low-
speed applications.
The digital filters absorb glitches on digital pins. For the port pin configured as a digital
pin, the digital filter is enabled for the pin if the associated bit is set in the port digital
filter enable register. For a port pin that is not configured for analog function, the digital
filter for the pin is disabled, and the associated bit in the port digital filter enable register
has no effect.
The width of the glitch to absorb can be specified in terms of number of filter clock
cycles. The bus clock or LPO clock can be selected as a filter clock that is configured by
the PTCLKS bit in the port digital filter control register. The width of the glitch to absorb
depends on the Filter Factor (FF) bits in the port digital filter control register. Effectively,
any down-up-down or up-down-up transition on the digital input line that occurs within
the number of clock cycles programmed by the filter factor is ignored by on-chip
modules. For details, see the description of the port digital filter control register.
Because the configuration of the port digital filter control register is for all digital filters
of the port, changing the port digital filter control register affects all digital filters of the
port if enabled. Configuration of the port digital filter control register must occur when
no digital filter is active (the port digital filter enable register is 00h).
The LPO clock can operate in stop mode; if the digital filter works in stop mode, the
PTCLKS bit must be set before the entry to stop mode.
46.4.4.1 Initialization of digital filters
When a digital filter for a port pin is enabled from a disabled state or pin control is
changed from one module to another module while the digital filter is active, some
enabled modules may get a false input. To prevent a false input to on-chip modules and
related errors during initialization of digital filters, you must do the following to enable
the digital filter for input of the target module:
Freescale Semiconductor, Inc.
1. Write 0 to the PTDFE bit to disable the digital filter for the pin, if it is active.
2. Write 0 to the PTIPE bit to disable the pin interrupt function, if it is enabled.
3. Disable other on-chip modules that have higher priority for pin control than the target
4. Write 1 to the associated pin enable bit of the target module, if it is not enabled.
module.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Chapter 46 Enhanced GPIO (EGPIO)
1205