mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1034

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Registers
42.3.8 I2C Range Address register (I2Cx_RA)
Addresses: I2C0_RA is FFFF_81C0h base + 7h offset = FFFF_81C7h
42.3.9 I2C SMBus Control and Status register (I2Cx_SMB)
1034
Reserved
Reset
Field
RAD
Read
7–1
Write
0
Bit
I2C1_RA is FFFF_81D0h base + 7h offset = FFFF_81D7h
I2C2_RA is FFFF_81E0h base + 7h offset = FFFF_81E7h
I2C3_RA is FFFF_81F0h base + 7h offset = FFFF_81F7h
A master assumes that the bus is free when detecting the clock
and data signals being high for greater than high time out
period. However, SHTF1 rises in bus transmission process with
idle bus state.
When TCKSEL is set, there is no meaning to monitor SHTF1
since the bus speed is too high to match the protocol of SMBus.
Range slave address
This field contains the slave address to be used by the I2C module. The field is used in the 7-bit address
scheme. Any nonzero value written enables this register. This register's use is similar to that of the A1
register, but in addition this register can be considered a maximum boundary in range matching mode.
This read-only bit is reserved and always has the value zero.
7
0
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
I2Cx_RA field descriptions
0
5
Preliminary
NOTE
NOTE
RAD
0
4
Description
0
3
0
2
Freescale Semiconductor, Inc.
0
1
0
0
0