mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 466

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mcf51jf128

Manufacturer Part Number
mcf51jf128
Description
Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Initialization / Application Information
466
Figure 20-15. Flowchart of BLPI to FEE Mode Transition using an 4 MHz crystal
g. At this point, by default, the C4[DRST_DRS] bits are set to 2'b00 and
C4[DMX32] is cleared to 0. If the MCGOUT frequency of 40 MHz is desired
instead, set the C4[DRST_DRS] bits to 0x01 to switch the FLL multiplication
factor from 640 to 1280. To return the MCGOUT frequency to 20 MHz, set
C4[DRST_DRS] bits to 2'b00 again, and the FLL multiplication factor will
switch back to 640.
S[OSCINIT] = 1 ?
IN BLPI MODE
C1 = 0x10
C2 = 0x1C
C2 = 0x00
CHECK
START
MCF51JF128 Reference Manual, Rev. 2, 03/2011
YES
NO
Preliminary
S[CLKST] = %00?
S[IREFST] = 0?
IN FEE MODE
CONTINUE
CHECK
CHECK
YES
YES
Freescale Semiconductor, Inc.
NO
NO

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