mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 700

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

CMP Functional Description
During operation, the propagation delay of the selected data paths must always be
considered. It can take many bus clock cycles for COUT and the CFR/CFF status bits to
reflect an input change or a configuration change to one of the components involved in
the data path.
When programmed for filtering modes, COUT will initially be equal to zero until
sufficient clock cycles have elapsed to fill all stages of the filter. This occurs even if
COUTA is at a logic one.
30.8.4 Low Pass Filter
The low-pass filter operates on the unfiltered and unsynchronized and optionally inverted
comparator output COUTA and generates the filtered and synchronized output COUT.
Both COUTA and COUT can be configured as module outputs and are used for different
purposes within the system.
Synchronization and edge detection are always used to determine status register bit
values. They also apply to COUT for all sampling and windowed modes. Filtering can be
performed using an internal timebase defined by FPR[FILT_PER], or using an external
SAMPLE input to determine sample time.
The need for digital filtering and the amount of filtering is dependent on user
requirements. Filtering can become more useful in the absence of an external hysteresis
circuit. Without external hysteresis, high frequency oscillations can be generated at
COUTA when the selected INM and INP input voltages differ by less than the offset
voltage of the differential comparator.
30.8.4.1 Enabling Filter Modes
Filter Modes are enabled by setting CR0[FILTER_CNT] greater than 0x01 and (setting
FPR[FILT_PER] to a non-zero value OR setting CR1[SE]=1). If using the divided bus
clock to drive the filter, it will take samples of COUTA every FPR[FILT_PER] bus clock
cycles.
The filter output will be at logic zero when first initalized, and will subsequently change
when CR0[FILTER_CNT] consecutive samples all agree that the output value has
changed. Said another way, SCR[COUT] will be zero for some initial period, even when
COUTA is at logic one.
Setting both CR1[SE] and FPR[FILT_PER] to 0 disables the filter and eliminates
switching current associated with the filtering process.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
700
Freescale Semiconductor, Inc.