mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1161

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Chapter 44 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
44.4
Functional description
44.4.1 SAI clocking
The SAI clocks include the audio master clock, the bit clock, and the bus clock.
44.4.1.1 Audio Master Clock
The audio master clock is used to generate the bit clock when the receiver or transmitter
is configured for an internally-generated bit clock. The transmitter and receiver can
independently select between the bus clock and up to three audio master clocks to
generate the bit clock.
Each SAI peripheral can control the input clock selection, pin direction and divide ratio
of one audio master clock. The input clock selection and pin direction cannot be altered if
an SAI using that audio master clock has been enabled. The master clock divide ratio can
be altered while an SAI is using that master clock, although the change in the divide ratio
takes several cycles. The divide update flag can be polled to determine when the divide
ratio change has completed.
The audio master clock generation and selection is chip specific. Refer to chip-specific
clocking information about how the audio master clocks are generated. A typical
implementation appears in the following figure.
Figure 44-41. SAI Master Clock Generation
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
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