mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 763

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
Field
TMS
TEN
TPS
TPP
TFC
5–4
3
2
1
0
Timer Pin Select
The Timer Pin Select configures the input source to be used in Pulse Counter mode. The Timer Pin
Select should only be altered when the LPTMR is disabled. The input connections vary by device. See the
Chip Configuration details for information on the connections to these inputs.
00
01
10
11
Timer Pin Polarity
The Timer Pin Polarity configures the polarity of the input source in Pulse Counter mode. The Timer Pin
Polarity should only be changed when the LPTMR is disabled.
0
1
Timer Free Running Counter
When clear the Timer Free Running Counter configures the LPTMR Counter Register to reset whenever
the Timer Compare Flag is set. When set, the Timer Free Running Counter configures the LPTMR
Counter Register to reset on overflow. The Timer Free Running Counter should only be altered when the
LPTMR is disabled.
0
1
Timer Mode Select
The Timer Mode Select configures the mode of the LPTMR. The Timer Mode Select should only be
altered when the LPTMR is disabled.
0
1
Timer Enable
When the Timer Enable bit is clear, it resets the LPTMR internal logic (including the LPTMR Counter
Register and Timer Compare Flag). When the Timer Enable bit is set, the LPTMR is enabled. When
writing 1 to this bit, bits LPTMR_CSR[5:1] should not be altered.
0
1
Pulse Counter input source is active high, and LPTMR Counter Register will increment on the rising
edge.
Pulse Counter input source is active low, and LPTMR Counter Register will increment on the falling
edge.
LPTMR Counter Register is reset whenever the Timer Compare Flag is set.
LPTMR Counter Register is reset on overflow.
Time Counter mode.
Pulse Counter mode.
LPTMR is disabled and internal logic is reset.
LPTMR is enabled.
Pulse counter input 0 is selected.
Pulse counter input 1 is selected.
Pulse counter input 2 is selected.
Pulse counter input 3 is selected.
LPTMRx_CSR field descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Description
Chapter 35 Low Power Timer (LPTMR)
763