mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 869

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

37.4.11.7 FTM Counter Synchronization
The FTM counter synchronization occurs when the FTM counter is updated with the
value of the CNTINH:L registers and the channel outputs are forced to their initial value
as defined by the channel configuration.
Freescale Semiconductor, Inc.
Figure 37-189. CHnOM Synchronization when (SYNCHOM = 1), (PWMSYNC = 0), and (a
Figure 37-190. CHnOM Synchronization when (SYNCHOM = 1), (PWMSYNC = 1), and (a
• If SYNCHOM = 1 and PWMSYNC = 1, then this synchronization is made on the
• If REINIT = 0, then this synchronization is made when the FTM counter changes
• If REINIT = 1 and PWMSYNC = 0, then this synchronization is made on the next
next enabled hardware trigger event. The trigger enable bit (TRIGn) is cleared when
the enabled hardware trigger n event is detected (refer to the following figure).
from MODH:L to CNTINH:L.
enabled trigger event. If the trigger event was a software trigger, then the SWSYNC
bit is cleared (refer to the following figure).
write 1 to TRIG0 bit
write 1 to TRIG0 bit
trigger 0 event
trigger 0 event
system clock
system clock
TRIG0 bit
TRIG0 bit
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Hardware Trigger Was Used)
Hardware Trigger Was Used)
Preliminary
CHnOM bit is updated and
CHnOM bit is updated and
TRIG0 bit is cleared
TRIG0 bit is cleared
Chapter 37 FlexTimer (FTM)
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